1. Field of the Invention
The present invention generally relates to computer packaging and, more particularly, to a high performance computer package characterized by a physical structure that matches the logical structure requirements providing multi-dimensional access to circuit components and interconnections in a dense packaging media with no cables.
2. Description of the Prior Art
Increasing demand for computer power has outstripped the capability of single processors (uniprocessors) to perform. High performance computers now require many processors operating in parallel and sharing the same main memory; i.e., so-called tightly coupled parallel processors. In addition, numerically intensive computing applications are growing, placing a requirement for data processing capability at very high speeds.
The basic organization of a tightly coupled multi-processor (MP) system comprises a plurality of processors which may be selectively connected to a plurality of independently addressable memory modules known as basic storage modules (BSMs). In a typical MP system, there may be N processors and M BSMs, where M is typically greater than N. Since all processors require equal access to the BSMs, there is some form of N.times.M switch, such as a cross-bar switch, which selectively connects a processor to an addressed BSM for storing and retrieval of data. The traditional manner of connecting the N processors and the M Memory Elements or BSM is by a central switch. This means that as wider data busses are required and there is a need for (N.times.Buss width in bits)+(M.times.Buss width in Bits) on the switch package.
The parameters of importance to the performance of the MP system are processor cycle time, bandwidth, electrical path length, round trip delay, and skew. The processor cycle time is minimized by placing the cycle determining path elements in the closest possible proximity to each other. The bandwidth between a processor and a BSM is maximized by using the fastest possible data rate over a large number of parallel connections between the processor and the switch and between the switch and the BSMs. The electrical path length is the length between data latching points on different, but interconnected, functional units as measured in nanoseconds (nsec.). The total round trip delay from a processor to an addressed BSM and back is known as the memory latency. This includes a number of electrical path lengths. The skew is the electrical path length differences due to variations in routing from one point to another. The area of memory is determined by the surface area required to contain the storage chips and the logic support chips.
In a known construction, referred to as "card-on-board" (COB) memory, all of the external interconnections are placed on one edge of the card. When the memory is accessed for data, a signal must travel from the input edge of the card to the far side and return back to the original edge. In so doing, it has traversed the width of the card twice, with attendant delay, and the required data appears at the same edge from which it was requested. It is evident in this conventional system, there is significant skew or difference in electrical path due to accessing different parts of the memory or different memory chips in different sections of the memory, or from different processors.
Any high performance computer package must have the capacity to provide the necessary functions, support the cycle time, and minimize the latencies between functions. As cycle times have been reduced below ten nsec., the classical method of using cables to communicate between packaged function has added dramatically to the storage latency. In addition, distances between functions have been such as to require that the communicating transmission lines store signals because their length produces a delay in excess of the cycle time. This not only degrades performance, it also forces wiring restrictions to prevent reflections from being coincident with the signal information content. Concurrent with faster cycle times is the need to support more bandwidth. A portion of this bandwidth can be derived from the faster cycle time and the remainder, from wider data busses. The effect of this is to require more logic and cables which have a tendency to move functions further apart, while at the same time the performance requires functions to be closer together. In addition, cables affect connector density spacing. High performance computers, such as supercomputers, accentuate all these effects in order to support parallel operations and to satisfy the demand for faster computing power along with the insatiable demand for data. This leads to cycle times quickly approaching one nanosecond and data bandwidths exceeding 100 giga bytes (GB) per second to support many processors operating simultaneously.